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56 weeks ago
Lead FPGA engineer on an internal R&D project
I was lucky enough to spend two years on the I&T team for the main computer subsystem for the Mars Science Laboratory. I will never forget those long days (and some nights) in the lab.
I followed up MSL by joining a small research team where I performed multiple functions as the lead ASIC layout engineer (five test chips with zero layout errors), test board designer and layout, proposal writing, conference submissions, and presenting research results to our external customers. This project taught me the value of sales and marketing for an engineer.
During my final year I also began providing FPGA support to various projects. I developed a parameterized FFT core and a specialized asynchronous FIFO that included unique data management.